| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 21 | Foreground Based Digital Domain Standardization of 16-Bit 1-MS/S SAR ADC Authors:D. SEKHAR, K. AMALA |
88-93 |
Download | |
| IJVDCS 22 | Implementation of Multiplier Accumulator for Energy Saving in Wireless Sensor Networks Authors:PANDIRI JAGADESWARI, YEDLA HARIKA |
94-98 |
Download | |
| IJVDCS 23 | Optimized Design of KSA And Sta For Improvement of Speed and Area in VLSI Systems Authors:MADDI JAYASRI, G M ANITHA PRIYADARSHINI |
99-102 |
Download | |
| IJVDCS 24 | High Speed and Compact Design of FIR Filter Baesd on Product Accumulation Section Authors:BANISETTI SOWJANYA, K. GOVINDARAO |
103-108 |
Download | |
| IJVDCS 25 | Implementation of Multiplier Accumulator for Energy Saving in Wireless Sensor Networks Authors:D. PRADEEP KUMAR, P. DALINAIDU |
109-112 |
Download | |
| IJVDCS 26 | High Speed And Area Efficient MAC Unit for Multiplier Authors:B. ASHA, R. SUMALATHA, K. VIJAYA PRASAD |
113-118 |
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| IJVDCS 27 | Design of Vedic Multiplier using Quaternary Signed Digit Number System for High Speed Applications Authors:B. DURGARAO, P. NAGA SRIKANTH, K. VIJAYA PRASAD |
119-124 |
Download | |
| IJVDCS 28 | Reconfigurable Cache Memory of RAM for Scratch PAD Memory Authors:SK. MAHAMMAD IRSHAD, NAGA BHUSHANAM, K. VIJAYA PRASAD |
125-131 |
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| IJVDCS 29 | High Speed Full And Half Adders using Highly Efficient XNOR And XOR Gates Authors:CH. JAYARAMA MOHANRAO, P. NAGA SRIKANTH, K. VIJAYA PRASAD |
132-136 |
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| IJVDCS 30 | Design of High Speed Comparator using Cross Coupled Transistors Authors:G. PRIYANKA GOWRI, NAGABHUSHAN BABU, K. VIJAYA PRASAD |
137-141 |
Download | |
